1. Field of the Invention
The present invention relates to a device which makes accurate measurements of speed of an elevator when it is moving in a relatively slow speed.
2. Description of the Related Art
An elevator controller 1 shown in FIG. 4 comprises a CPU 2, a ROM 3, a RAM 4, an interface circuit 5 for input and output signals, and a speed detector circuit 6. Also shown in FIG. 4 are a motor 7, an elevator box 8, a counter-weight 9, and a pulse generator 10 which generates, depending on the rotation of the motor 7, two kinds of pulses 90.degree. apart in phase with each other, i.e., A phase and B phase pulses.
FIG. 5 is a more detailed diagram of the speed detector circuit 6. FIG. 5 shows A phase pulse 10a, B phase pulse 10b, an up/down counter 11 which counts rising edges of the pulse 10a, a direction discriminator 12 which identifies the direction of travel of an elevator from the A phase pulse 10a and the B phase pulse 10b, a timer counter 13 which measures time by counting an external clock signal, latch circuits 14 and 15 arranged to the output of the timer counter 13, gate circuits 16 and 17 arranged respectively to each output of the up/down counter 11 and the latch circuit 15, and a data bus 18 for the CPU 2.
Referring now to FIG. 6 and FIG. 7, the operation of this prior art is described below. When the elevator box 8 begins moving, i.e., the motor 7 is put into motion, the pulse generator 10 outputs the A phase pulse 10a and the B phase pulse 10b, both of which are 90.degree. apart with each other, in accordance with the rotation of the motor 7. Each of these pulses is fed to the speed detector circuit 6 in the elevator controller 1. Receiving data from the speed detector circuit 6, the CPU 2 computes the travel speed of the elevator box 8 as described below, according to a predetermined program.
Two phase pulses, 10a and 10b, fed to the speed detector circuit 6 are input to the direction discriminator 12, where the direction of travel of the elevator is determined. The speed detector circuit 6 outputs up/down signal 12a which indicates the direction of travel of the elevator. The up/down counter 11 is driven by the up/down signal 12a and the rising edge of the pulse 10a. The timer counter 13 normally counts up a predetermined clock signal CLK, and the latch circuit 14 latches the count of the timer counter 13 at the timing of each rising edge of the A phase pulse 10a. An example of the time chart of this operation is illustrated in FIG. 6.
Since each of the A phase pulse 10a and the B phase pulse 10b is provided by the pulse generator 10 in response to the rotation of the motor 7, a distance of travel L of the elevator box 8 per pulse may be defined. The up/down counter 11 counts up or down at the timing of each rising edge of the A phase pulse, i.e., at time a, time b and time c. Assuming that the count is m at time a with the counter counting up, the count should be m+1 and m+2 at time b and time c, respectively. The timer counter 13 latches, at the timings of a, b and c, its counts (respectively designated x, y and z) into the latch 14.
The description that follows is how the CPU 2 determines the speed of the elevator. The CPU 2 normally performs its task according to a predetermined arithmetic cycle. The CPU read cycle, during which the count of the up/down counter 11 and the count of the timer counter 13 are read, and which is represented by a duration from d to e in FIG. 5, is substantially constant. When the CPU 2 is reading data at time d and time e as shown in FIG. 6, the count of the up/down counter 11 is m at time d, and m+2 at time e. The distance of travel X of the elevator box 8 is expressed by the following equation. EQU X={(m+2)-m}.times.L=2L (1)
An elapsed time T required for the distance of travel X is expressed as follows: EQU T=(z-x)t (2)
where t represents the period of the clock signal CLK. The speed of the elevator box 8, i.e., the speed V of the elevator is given as follows: EQU V=2L/(z-x)t (3)
When the speed is increased, the number of pulse count of the A phase pulse increases during the duration from time d to time e, the same process is also applicable to determine the speed.
The count of the timer counter 13 is latched at the timing when data is read from the up/down counter 11 by outputting read signal RDOL. This is for the purpose of retaining the count of the timer counter 13 at the timing of read. Therefore, read operation is performed at time d in FIG. 6, the reading of the count x of the timer counter 13, corresponding to the count m of the up/down counter 11, is reliably done.
Conventional elevator speed detector devices are constructed as described above. When the speed of travel of the elevator is slowed down, the number of rising edges of the A phase pulse included in the predetermined duration of CPU data read cycle are decreasing, possibly leading to no rising edge state. In such a slow travelling speed region, when a rising edge such as P1 in FIG. 7 takes place immediately after the CPU reading operation, its detection may be delayed for a duration corresponding to one data read cycle. When no rising edge takes place as illustrated by P2 in FIG. 7, no change occurs during the data read cycle, thereby no accurate speed measurements are made throughout this period.